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2025-04-27
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WSL
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labeling
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chisel
chiselto generate verilog code… workflow is : 123sudo pacman -S sbt jdk-openjdk verilatorgit clone https://github.com/chipsalliance/chisel-template.git MyChiselProject then we get a directory MyChiselProject. the code write in : MyChiselProject/src/main/scala you can create a folder here, like example, then write code in the example folder. after done, back to the root path of the MyChiselProject , run : 12sbt "runMain example.Elaborate"(if your chisel file is named...
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cmake
cmakewindows: 1234567cmake -G “MinGW Makefiles” // mingw32-makecmake -G Ninja // ninjacmake -G “Unix Makefiles” // clangcmake -G "MinGW Makefiles" -S .. -B . -DCMAKE_C_COMPILER=<path to gcc.exe> -DCMAKE_CXX_COMPILER=<path to g++.exe> command lines homepageclick here to come back to command line homepage.
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conda
condacreate and delete env: 123conda create -n <envname> python=3.10conda remove --name <envname> --all do not auto-use base: 1conda config --set auto_activate_base false enter/quit env: 1conda activate <envname> / deactivate env package: 12345(pip install conda-pack)conda package -n <envname>tar -xzvf <envname>.tar.gz -C path/to/store.tar.gz export/import(in env): 123conda env export > environment.ymlconda env create -f environment.yml also...
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