欢迎来到从零开始的DFT工程师第三期。

这里我们进行EDA+UVM的学习。参考的内容依旧是chipverify的相关指导书，链接在这里。

其余可供参考的资料如下：

UVM?

UVM是指Universal Verification methodology，是一种通用且规范化的验证方法。也可以说是一个用于验证测试的框架或者是库，学习UVM的前提是systemverilog.

UVM包含在很多商业或者开源软件工具中，比如说cadence, synopsys, mentor graphics
questa，当然也可以直接下载UVM标准库，体积很小，可以用于学习，但是商业软件的框架流程一般更加成熟。

如果懒得配置商业软件的话可以去Accellera选择想要的版本下载，只需要解压之后在rc文件里面加入路径export UVM_HOME=<path to uvm-core-xxxx>即可。

简单的测试

首先来测试一下环境是否正常。我这里是在虚拟机下运行的synopsys VCS工具，具体版本信息如下：

虚拟机OS为CentOS，内核版本为3.10.0-1160.119.1.el7.x86_64, synopsys 版本为2018.09.

安装方法具体可见本系列之前的一篇。

准备三个文件，top.sv, env.sv, test.sv, 还有一个测试脚本run.sh,具体作用之后再说，内容如下：

top.sv:

1
2
3
4
5
6
7
8
9
10
11
12


import uvm_pkg::*;

`include "uvm_macros.svh"

module top;
    initial begin
        run_test("my_test");
    end
endmodule

test.sv:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

class my_test extends uvm_test;

    `uvm_component_utils(my_test)

    my_env env;

    function new (string name, uvm_component parent);
        super.new(name, parent);
    endfunction

    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        env =my_env::type_id::create("env", this);
    endfunction


endclass

env.sv:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
class my_env extends uvm_env;
    `uvm_component_param_utils(my_env)

    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction : new

    function void build_phase (uvm_phase phase);
        super.build_phase(phase);
    endfunction : build_phase

    task run_phase (uvm_phase phase);

        phase.raise_objection(this);

        set_report_verbosity_level (UVM_MEDIUM);
        uvm_report_info (get_name(), $sformatf("Hello UVM!!!!!"), UVM_MEDIUM, `__FILE__, `__LINE__);
        `uvm_info (get_name(), $sformatf("Finishing."), UVM_LOW);

        phase.drop_objection(this);
    endtask : run_phase
endclass : my_env

run.sh:

1
2
3
4
5
6

vcs -full64 -sverilog \
	+vpi \
	-ntb_opts uvm \
	top.sv env.sv test.sv 2>&1 | tee compile.log

之后直接运行run.sh，运行结果如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
                         Chronologic VCS (TM)
       Version O-2018.09-SP2_Full64 -- Sun Dec 21 20:41:05 2025
               Copyright (c) 1991-2018 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm/uvm_pkg.sv'
Parsing included file '/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm/uvm_macros.svh'.
...
...
...
Back to file 'top.sv'.
Parsing design file 'env.sv'
Parsing design file 'test.sv'
Top Level Modules:
       top
No TimeScale specified
Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared  -Bsymbolic  -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
rm -f _csrc0.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -rdynamic  -Wl,-rpath=/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib -L/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib  /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib/vpdlogstub.o uvm_dpi.o     _4568_archive_1.so _prev_archive_1.so _csrc0.so  SIM_l.o  _csrc0.so    rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive       ./../simv.daidir/vc_hdrs.o    /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o -ldl  -lc -lm -lpthread -ldl
../simv up to date
CPU time: 3.103 seconds to compile + .152 seconds to elab + .240 seconds to link

之后运行simv文件，结果如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Dec 22 17:22 2025
----------------------------------------------------------------
UVM-1.1d.Synopsys
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO env.sv(17) @ 0: uvm_test_top.env [env] Hello UVM!!!!!
UVM_INFO env.sv(18) @ 0: uvm_test_top.env [env] Finishing.
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm/base/uvm_objection.svh(1273) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :    4
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[TEST_DONE]     1
[env]     2
$finish called from file "/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm/base/uvm_root.svh", line 439.
$finish at simulation time                    0
           V C S   S i m u l a t i o n   R e p o r t
Time: 0
CPU Time:      0.230 seconds;       Data structure size:   0.2Mb
Mon Dec 22 17:22:34 2025

发现在env.sv里面写的uvm_report_info(get_name(), $sformatf("Hello UVM!!!!!"), UVM_MEDIUM, FILE, __LINE__);成功输出UVM_INFO env.sv(17) @ 0: uvm_test_top.env [env] Hello UVM!!!!!，则证明软件安装无误。

另外补充一下运行命令

运行编译的主要命令是vcs，还有一些常用参数如下：

parameter description
-full64 以64位环境运行，当前多数机器都要加
-sverilog 开启对于systemverilog的支持
-ntb_opts 指定uvm标准版本号，比如uvm-1.2就是选定1.2标准
-debug_acc+all 开启所有调试权限，允许仿真时查看信号和单步调试
-debug_region+cell+lib 指定部分区域开启调试能力
-kdb 生成knowledge database, 将仿真数据同步到verdi进行交互式调试

还有一些在特定情况完成特定目的会用到的：

parameter description
关于编译加速和效率 compilation speed
-j8 调用多核并行编译,8指的是CPU核心数
-Mupdate 增量编译，再次编译的时候只会编译改动过的部分
-v 指定库文件，一般用于添加某些厂商专供的仿真模型
-y 指定库目录，可以用来寻找缺失的模块定义
代码覆盖率 coverage
-cm 开启覆盖率收集，一般有line(行), cond(condition条件), fsm(finite state machine有限状态机), tgl(翻转), branch(分支)
-cm_name 给当前生成的覆盖率文件命名
-cm_dir 指定覆盖率数据库保存的目录
其他关键参数 others
-timescale=1ns/1ps 如果代码里没写可以在参数里面写
-top 显示指定顶层文件
-f <file.list> 指定一个包含所有源文件路径的列表文件，用于管理大型项目
-l 把日志输出到指定文件

好的我们正式开始

UVM是出于进行自动化验证的需求产生的，本质上是systemverilog的一组API，用来帮助我们创建高效的验证环境，由Accellera维护标准。

UVM　classes

正如之前所说，UVM本身是一组API，他包含了很多base class供我们使用，之后的环境搭建完成测试等很多步骤都需要继承UVM的基类。

UVM base classes可以分为三大类，uvm_object, uvm_transcation, uvm_component.

uvm_object

uvm_object是UVM中所有可操作对象的基类，这里面定义了很多objects的通用操作，包括create,　copy, clone, compare, print, record等，而且自带objects的身份信息，比如name,　typename, unique id等。

uvm_transaction

uvm_transcation可以用于生成激励，分析检查结果。

uvm_component

组件是贯穿仿真过程的准静态对象，每个uvm_component可以通过（唯一的）分层路径名称被找到;
uvm_component定义了分阶段的测试流程，每个阶段都是被一个按照精确顺序运行的callback定义的；此外uvm_component还定义了配置，报告，事务记录，工厂接口。

UVM testbench architecture

UVM testbench是通过继承uvm classes来创建的。

UVM testbench hierarchy

一般的testbench结构是这样的：
testbench architecture

他的层级结构是：

test -> env -> agent -> sequencer/driver/monitor

transaction flow:
激励: sequence -> sequencer -> driver -> DUT
观测：DUT -> monitor -> scoreboard/coverage/ref model

test

test层级，通常是做三件事：

  • 配置testbench：设置config_db, 传递虚接口…
  • 启动层级构建：build_phase ….
  • 启动激励：开始创建激励信号并且控制仿真结束。

env

env的主要作用就是把agent, scoreboard, coverage, reference model等拼装为一个整体。

build_phase, connect_phase 都是这里完成。

agent

作用是把某个接口相关的组件打包。

sequence_item

从激励侧来说，sequence 产生item, driver使用item的字段驱动DUT;
从观测侧来说，monitor把DUT上看到的pin波形抽象成item，发送给scoreboard.

driver

从sequencer 拿到 sequence_item并且执行相关时序操作，在接口上产生pin-level的信号。

sequence

sequence是产生transcation的脚本，他用来按照顺序发送带约束/随机化的item.

sequencer

sequencer是仲裁/路由中心，连接sequence和driver，负责进行对多个sequence同时发送请求时进行仲裁，把sequence_item送到driver，有时把driver的response返回给sequence.

monitor

monitor的作用就是观测pin-level的接口信号，把相关信息解析成transaction，通过analysis_port发送出去。

monitor.analysis_port -> scoreboard, monitor.analysis_port -> coverage collector, monitor.analysis_port -> reference model

scoreboard

用来检测功能是否正确，将接受到的transaction和期望值对比。

期望值一般是通过reference model生成正确的结果，或者是golden reference（预先确定好的正确结果）

UVM_Sequence_item

sequence_item是通过继承uvm_sequence_item来生成的。继承路线是：uvm_object ->
uvm_transcation -> uvm_sequence_item.

uvm_object里面会定义很多virtual method和macro，这些可以让之后的uvm_sequence_item更加具有普适性。

UVM utility macros

工具宏提供了create method（用于clone）和get_type_name method（用于debugging）.

UVM Field marcos

在进行类型注册的时候，如果你写的是：

1
`uvm_object_utils(TYTPE)

那就不能直接用相关的字段自动化（field automation, 比如print()　就只输出类型/对象名，不能自动把成员变量展开输出）

但是如果写：

1
2
3
`uvm_object_utils_begin(TYPE)
    `uvm_field_*(FIELD, FLAG)
`uvm_object_utils_end

这样就会把field automation注册进去，之后相关的copy/compare/pack/print/record等操作就可以自动按照字段工作。

FIELD参数通常就是class里面的class member; FLAG具体就有很多，如下：

FLAG description
UVM_ALL_ON set all operations on default
UVM_DEFAULT use the default flag settings
UVM_NOCOPY 请勿COPY此字段
UVM_NOCOMPARE 请勿比较此字段
UVM_NOPRINT 请勿打印此字段
UVM_NODEFPRINT 如果此字段和其他字段不同，才打印
UVM_NOPACK 不要pack or unpack这个字段
UVM_PHYSICAL treat as physical field.
UVM_ABSTRACT treat as an abstract field.
UVM_READONLY 不允许用set_*_local设置这个字段

关于输出格式，还有以下参数：

FLAG description
UVM_BIN print/record the field in binary
UVM_DEC print/record the field in decimal
UVM_UNSIGNED print/record the field in unsigned decimal
UVM_OCT print/record the field in octal
UVM_HEX print/record the field in hexadecimal
UVM_STRING print/record the field in string format
UVM_TIME print/record the field in time format

sequence item

sequence-item包含了生成激励所需要的数据字段。

为了生成激励，sequence中的sequence-item通常是随机的，因此sequence-item应该是声明为rand，同时可以被约束。

data field一般会有一下类型的信息：

  • control information: 表示传输方式，传输大小
  • payload information: 表示传输的数据内容
  • configuration information:表示配置信息，工作模式，错误行为等
  • analysis information:用于捕获被测信息，比如读取数据和响应。

除了analysis一般不会配置成rand，另外三个一般作为stimulus，所以经常是rand+constraints.

sequence item example

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
import uvm_pkg::*;
`include "uvm_macros.svh"
class mem_seq_item extends uvm_sequence_item;
    //control information
    rand bit [3:0] addr;
    rand bit wr_en;
    rand bit rd_en;

    //payload information
    rand bit [7:0] wdata;

    //analysis information
    bit [7:0] rdata;

    //utility and field macros
    `uvm_object_utils_begin(mem_seq_item)
        `uvm_field_int(addr, UVM_ALL_ON)
        `uvm_field_int(wr_en, UVM_ALL_ON)
        `uvm_field_int(rd_en, UVM_ALL_ON)
        `uvm_field_int(wdata, UVM_ALL_ON)
    `uvm_object_utils_end


    //constructor
    function new(string name = "mem_seq_item");
        super.new(name);
    endfunction

    //vonstraints, to generate any one among write and read
    constraint wr_rd_c {wr_en != rd_en;};
endclass

UVM sequence item methods

create(): create method allocates a new object(same type as input), return via a base uvm_object handle.

一个测试：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
module seq_item_tb;
    mem_seq_item seq_item;

    initial begin
        //create method
        seq_item = mem_seq_item::type_id::create();

        //randmizing the seq_item
        seq_item.randomize();

        //printing the seq_item
        seq_item.print();
    end
endmodule

run: vcs -full64 -sverilog -ntb_opts uvm-1.2 mem_seq_item.sv -R
输出结果是：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 14 22:54 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

---------------------------------------
Name          Type          Size  Value
---------------------------------------
mem_seq_item  mem_seq_item  -     @335
  addr        integral      4     'h9
  wr_en       integral      1     'h1
  rd_en       integral      1     'h0
  wdata       integral      8     'h6c
---------------------------------------
           V C S   S i m u l a t i o n   R e p o r t
Time: 0
CPU Time:      0.210 seconds;       Data structure size:   0.2Mb
Wed Jan 14 22:54:54 2026

copy: copy make a object a copy of the specified object.

一个测试：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
module seq_item_tb;
    //instance
    mem_seq_item seq_item_0;
    mem_seq_item seq_item_1;

    initial begin
        //create method
        seq_item_0 = mem_seq_item::type_id::create("seq_item_0");
        seq_item_1 = mem_seq_item::type_id::create("seq_item_1");

        seq_item_0.randomize();
        seq_item_0.print();

        //copy method
        seq_item_1.copy(seq_item_0);
        seq_item_1.print();
    end
endmodule

输出结果如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 14 22:59 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_0  mem_seq_item  -     @335
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_1  mem_seq_item  -     @339
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
           V C S   S i m u l a t i o n   R e p o r t
Time: 0
CPU Time:      0.150 seconds;       Data structure size:   0.2Mb
Wed Jan 14 22:59:40 2026

clone(): clone = create() + copy().

compare(): compare method是将数据对象的成员和右侧()提供的对象进行比较，匹配返回1, 否则返回0.

一个测试：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

module seq_item_tb;
    //instance
    mem_seq_item seq_item_0, seq_item_1;

    initial begin
        //create method
        seq_item_0=mem_seq_item::type_id::create("seq_item_0");
        seq_item_1=mem_seq_item::type_id::create("seq_item_1");

        //mismatch case
        seq_item_0.randomize();
        seq_item_1.randomize();

        seq_item_0.print();
        seq_item_1.print();

        if(seq_item_0.compare(seq_item_1))
            `uvm_info("", "seq_item_0 match with seq_item_1.", UVM_LOW)
        else
            `uvm_error("", "seq_item_0 is not match with seq_item_1.");




        seq_item_1.copy(seq_item_0);


        seq_item_0.print();
        seq_item_1.print();


        if(seq_item_0.compare(seq_item_1))
            `uvm_info("", "seq_item_0 match with seq_item_1.", UVM_LOW)
        else
            `uvm_error("", "seq_item_0 is not match with seq_item_1.");


    end



endmodule

输出结果是：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 15 10:54 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_0  mem_seq_item  -     @335
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_1  mem_seq_item  -     @339
  addr      integral      4     'h7
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h14
-------------------------------------
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_comparer.svh(351) @ 0: reporter [MISCMP] Miscompare for seq_item_0.addr: lhs = 'h9 : rhs = 'h7
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_comparer.svh(382) @ 0: reporter [MISCMP] 1 Miscompare(s) for object seq_item_1@339 vs. seq_item_0@335
UVM_ERROR test.sv(53) @ 0: reporter [] seq_item_0 is not match with seq_item_1.
-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_0  mem_seq_item  -     @335
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_1  mem_seq_item  -     @339
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
UVM_INFO test.sv(66) @ 0: reporter [] seq_item_0 match with seq_item_1.
           V C S   S i m u l a t i o n   R e p o r t
Time: 0
CPU Time:      0.200 seconds;       Data structure size:   0.2Mb
Thu Jan 15 10:54:03 2026

pack(), pack_bytes(), pack_ints(): pack可以把对象的属性按(bits, bytes, ints)拼接成array。

unpack(), unpack_bytes(), unpack_ints(): unpack可以按照对应的方式提取array中的数据。

使用方式：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
module seq_item_tb;
    //instance
    mem_seq_item seq_item_0, seq_item_1;
    bit bit_packed_data[];

    initial begin
        //create method
        seq_item_0=mem_seq_item::type_id::create("seq_item_0");
        seq_item_1=mem_seq_item::type_id::create("seq_item_1");

        //pack
        seq_item_0.randomize();
        seq_item_0.print();

        seq_item_0.pack(bit_packed_data);

        foreach(bit_packed_data[i])
            `uvm_info("PACK", $sformatf("bit_packed_data[%0d] = %b",i,bit_packed_data[i]), UVM_LOW)


        //unpack
        `uvm_info("UNPACK", "Before unpack",UVM_LOW)
        seq_item_1.print();

        seq_item_1.unpack(bit_packed_data);

        `uvm_info("UNPACK", "After unpack",UVM_LOW)
        seq_item_1.print();



    end

endmodule

输出结果是：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 15 11:45 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_0  mem_seq_item  -     @335
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[0] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[1] = 0
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[2] = 0
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[3] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[4] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[5] = 0
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[6] = 0
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[7] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[8] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[9] = 0
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[10] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[11] = 1
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[12] = 0
UVM_INFO test.sv(51) @ 0: reporter [PACK] bit_packed_data[13] = 0
UVM_INFO test.sv(55) @ 0: reporter [UNPACK] Before unpack
-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_1  mem_seq_item  -     @339
  addr      integral      4     'h0
  wr_en     integral      1     'h0
  rd_en     integral      1     'h0
  wdata     integral      8     'h0
-------------------------------------
UVM_INFO test.sv(60) @ 0: reporter [UNPACK] After unpack
-------------------------------------
Name        Type          Size  Value
-------------------------------------
seq_item_1  mem_seq_item  -     @339
  addr      integral      4     'h9
  wr_en     integral      1     'h1
  rd_en     integral      1     'h0
  wdata     integral      8     'h6c
-------------------------------------
           V C S   S i m u l a t i o n   R e p o r t
Time: 0
CPU Time:      0.190 seconds;       Data structure size:   0.2Mb
Thu Jan 15 11:45:13 2026

UVM sequence

sequence用来生成一系列的sequence-item，并且通过sequencer发送到driver(或者反向发送)。sequence是通过继承uvm_sequence生成的。

sequence是被sequence-item作为参数配置的，这会决定发送向/接收自driver的item的类型。

sequence base class

uvm_sequence的定义是这样写的：

1
2
virtual class uvm_sequence #(type REQ=uvm_sequence_item, type RSP=REQ) extends uvm_sequence_base

那么我们定义一个sequence的时候就可以这么写：

1
2
3
class write_sequence extends uvm_sequence #(mem_seq_item);

endclass

含义为write_sequence接收和发送的类型都是mem_seq_item.

req: a transcation that provides information to initiate th processing of
a particular operation.

rsp:a transcation that provides information about the completion or status of
a particular operation.

sequence execution

sequence最重要的两个属性是body method和m_sequencer handle.

body method定义了sequence的具体功能，m_sequencer handle包含了正在运行的sequence的引用，这些会对sequencer可见。

当测试中调用了the start of sequence，sequence就会被执行。

1
sequence_name.start(sequencer_name);

指明了sequence_name需要运行在sequencer_name上。

uvm_sequence中定义了会用到的methods, macros, callbacks,　当然我们也可以自己定义callback具体执行什么操作，这些method会在调用start of　sequence时自动执行。

sequence
mid_do和post_do是function, 其他是task.

sequence和driver之间的通信大致是这样的步骤：

  1. 创建request;
  2. 等待sequencer仲裁;
  3. （根据约束）随机化request;
  4. 发送request;
  5. 等待完成具体工作;
  6. 获取回应。

UVM sequence methods

具体函数接口如下：

method call description
create_item(req)
req=my_item::type_id::create(“req”);		 在内存中实例化一个transcation对象
wait_for_grant(); 请求仲裁。告知sequencer需要发送一个包，sequencer来完成调度仲裁
req.randomize(); 随机化，一般都有约束，一个可能的用法是`assert(req.randomize() with {});
send_request(req); 将已经完成随机化的数据包发送到sequencer的队列中。
wait_for_item_done(); 阻塞等待driver的反馈
get_response(rsp); 获取从driver发回的响应

具体代码展示如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
class mem_sequence extends uvm_sequence #(mem_seq_item);

    `uvm_object_utils(mem_sequence)

    //constructor
    function new(string name = "mem_sequence");
        super.new(name);
    endfunction


    virtual task body();

    req=mem_seq_item::type_id::create("req");
    wait_for_grant();
    assert(req.randomize());
    send_request(req);
    wait_for_item_done();
    get_response(rsp);

    endtask


endclass

UVM sequence macros

macros用于开启sequence，运行在sequencer上面的事务，默认的sequencer是m_sequencer.

macros description
`uvm_do(item/seq) seq_item或者是sequence作为参数，这个命令会执行上面定义的六个步骤（5和6是默认不定义的，只有手动定义了才会自动执行）
`uvm_create(item/seq) 创建item或者sequence
`uvm_send(item/seq) 跳过创建和随机化的步骤，执行剩余步骤
`uvm_rand_send(item/seq) 跳过创建步骤，执行剩余步骤
`uvm_do_with(item/seq, constraints) 根据第二个参数传入的约束，执行上面的六步
`uvm_rand_send_with(item/seq, constraints) 跳过创建，按约束执行剩余步骤
`uvm_do_pri(item/seq, priority) 按照priority执行以上六步
`uvm_do_pri_with(item/seq, constraints,priority) 按照约束和优先级执行以上六步
`uvm_send_pri(item/seq, priority) 跳过创建和随机化，按照优先级执行剩余步骤
`uvm_declare_p_sequencer(SEQUENCER) 声明一个p_sequencer,类型由SEQUENCER指定，通过使用p_sequencer的句柄可以访问sequencer的属性

用法如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

class mem_sequence extends uvm_sequence #(mem_seq_item);

    `uvm_object_utils(mem_sequence)

    //constructor
    function new(string name = "mem_sequence");
        super.new(name);
    endfunction


    virtual task body();

    //req=mem_seq_item::type_id::create("req");
    //wait_for_grant();
    //assert(req.randomize());
    //send_request(req);

    `uvm_do(req);
    //wait_for_item_done();
    //get_response(rsp);

    endtask


endclass

只是不需要反馈的时候这样写，但是如果要读取响应，就必须指明写上后面两句。

difference between m_sequencer and p_sequencer

m_sequencer handle中会包含正在运行的seuqence的引用，提供给sequencer;

p_sequencer是一个变量，他本身作为一个用来访问sequencer属性的handle.

UVM sequence Control

macros是分层次的，`uvm_do是一个高层的macro,很简单，但是无法细粒度地控制流程；wait_for_grant()之类的是底层的macro，可以很极限地插入控制，但是很多时候没有必要，所有更多时候还是使用中层的API.

standard API 中层API

主要是将整个过程简化为两个主要的原子操作。

  1. start_item(req):包含了两个动作：create_item+ wait_for_grant，如果对象没有创建，就会保证已经创建；之后向sequencer申请仲裁，直到driver准备好接受数据才会停止阻塞。

  2. 在start_item(req)返回之后，这时当前程序拥有对req的完全控制权，此时可以进行晚随机化(Late Randomization), 或者对其进行修改。

  3. finish_item(req): 封装了send_request + wait_for_item_done, 将包发给driver, 再阻塞等待，直到driver发回完成信号。

必须谈的一些场景

Late Randomization:如果在start_item之前随机化，可能要等很久才能得到仲裁许可发送，等发送的时候DUT的状态早就变了。所以是等拿到授权之后才随机化，保证当前的req是根据当下的电路状态的约束生成的。

Response Handling: 当driver完成任务后，它可以把结果通过rsp发回，可以在finish_item(req)之后get_response(rsp)获取，也可以设置set_response_queue_depth()，如果sequence处理慢，可以让sequencer暂存这些rsp.

关于一些坑

每一个req都有一个transaction_id, 当driver返回rsp，必须保证rsp.set_id_info(req)被调用.　如果是在sequence里面调用的get_response(rsp), UVM会检查返回的ID, 如果ID没有对上，就会导致sequence一直被阻塞等待获取一个不可能出现的包。

UVM sequencer

sequencer控制sequence和driver之间的req和rsp工作流，sequencer和driver之间使用TLM interface来进行transcation的交流，在编写代码的时候，uvm_sequencer有一个定义seq_item_export，uvm_driver有一个相对的定义seq_item_port，我们需要手动通过TLM connect method把他们连接起来。

1
driver.seq_item_port.connect(sequencer.seq_item_export);
1
2
3
4
5
6
7
8
class mem_sequencer extends uvm_sequencer#(mem_seq_item);

    `uvm_sequencer_utils(mem_seq_item);

    function new(string name, uvm_component parent);
    super.new(name, parent);
    endfunction:new
endclass:mem_sequencer

:new 是一个标签，在UVM的component中，他其实是可选的。但是为了代码规范和可读性一般都会写。原因是uvm_sequencer继承自uvm_component, 在整个仿真阶段一直存在。
:new有两个强制参数，string_name（组件的名字）和uvm_component parent（指向他的父节点）。没有parent的参数，sequencer无法在UVM的树状层级结构中找到自己的位置。
相对来说，sequence和item本身由于生命周期很短，用完即毁的，也不属于component
tree(hierarchy)的一部分，也不需要parent参数，就不写:new.

UVM config database

configuration database提供了对于集中式数据库的访问，而可以接收或者发送指定类型的数据。config_db 可包含标量对象，类句柄，列表，队列，虚接口等。database有名称表和类型表，每个资源都会存入这两个表，database是global access的，数据可以根据name和type进行检索获取。

UVM database get and set

分别可以使用uvm_config_db::get和uvm_config_db::set检索和存储信息。

配置数据库的方法：

1
2
bit uvm_config_db#(type T=int)::get(uvm_component cntxt, string inst_name,
string fiel_name, ref T value);
1
2
void uvm_config_db #(type T=int)::set(uvm_component cntxt, string inst_name,
string field_name, T value);

T 是存储的数据类型，cntxt是数据条目可访问的层级起点，inst_name是一条限制了数据条目可访问性的层级路径，field_name是数据条目的用于查询的标签，value是具体存储的值；对于get，成功会返回1,否则返回0.

其中inst_name是类似这样写的：top.env.agent.monitor

top.*:代表所有顶层是top的scopes(top内所有的)；
top.env.*.monitor:代表env内，所有以monitor结尾的scopes;

uvm_config_db set code

1
2
mem_if intf(clk, reset);
uvm_config_db#(virtual mem_if)::set(null, "*", "mem_intf", intf);

uvm_config_db get code

1
2
3
4
5
virtual interface mem_if mem_vif;

if(!uvm_config_db#(virtual mem_if)::get(this, "*", "mem_intf", mem_vif))
    `uvm_fatal(get_full_name(), {"virtual interface must be set
for:",".mem_vif"});

UVM phase

UVM phase是UVM env的一种同步机制，phase由callback method表示。

uvm_component提供了一组预先定义好的phase和对应的callback. callback method 可以是函数或者任务。从uvm_component派生的类都可以实现（部分或者全部）callback的执行，callback执行时会按照特定的顺序。

UVM phase主要是以下几个：

  • build
  • connect
  • end of elaboration
  • start of simulation
  • run
  • extract
  • check
  • report

其中run phase是task，其他一般都是function.

phase一般分为阶段：

build stage

一般认为build phase, connect phase, end_of_elaboration phase属于build stage(这么叫确实很奇怪而且其实原文是build_phase 属于 build phase，这一段概念可能会有一些混乱，只要理解这里分三个阶段，每个阶段做的事情不同就可以了，这里为了区分我把标题三个阶段改成stage用来区分，但是实际上写代码写的是build phase, run phase, clean up stage)。

这一阶段的phase是在testbench开始模拟的时候执行的，在这一阶段内，testbench components被创建，配置，互联。此阶段所有phase都是function,在0模拟时间内就完成构建。

run-time stage

start of simulation phase, run phase这两者一般认为是run-time stage, 这个stage是从模拟开始一直执行到模拟结束。其中的run phase是会消耗模拟时间的。

clean up stage

extract phase, check phase, report phase(and final phase)属于clean up stage.
在这一阶段，仿真的结果会被收集并且提供报告。

此处提供一个phase description:

phase description execution order
build 创建testbench的组件 top-down
connect 连接组件的TLM端口 bottom-up
end of elaboration 在开始模拟之前最后一次对测试结构，配置，连接性等进行调整 bottom-up
start of simulation 输出testbench的拓扑信息，配置信息 bottom-up
run 完成激励生成，驱动，检测，检查 parallel
extract 检索和处理scoreboard和fucntional coverage monitor的信息
check 检测DUT的行为是否正确以及testbench测试过程中出现的问题
report 展示模拟的结果，或者将其存入文件
final 完成其他testbench还未完成的活动

* inside UVM run phase

run phase还有以下不同的阶段:

inside run phase description
pre_reset pre_reset和run phase同时启动，他的作用是处理所有reset之前应该做的事情
reset 完成DUT和interface在复位时需要进行的具体行为
post_reset 用于下一次复位之后需要立即进行的所有活动做准备
pre_configure pre_configure用于复位完成之后，为DUT的配置过程中需要进行的所有活动做准备
configure 为了进行下一次模拟测试，对所有的DUT和memory进行处理(program DUT and any memories in the testbench so that for the next testcase)
post_configure post_configure等待DUT被完全配置好的信号到来，或者等待testbench进入ready to start the main test simulation的state
pre_main pre_main 被用来确保所有需要使用的组件都已经准备好产生激励了
main main 这一段时间被用来生成test case并且把它应用于DUT.当所有的激励用完，或者测试超时，就会结束
post_main 用于完成所有上一步骤中所有活动的最终处理
pre_shutdown 这一步的主要工作是确保所有生成的激励都通过了DUT，并且所有的结果信息都已经被从DUT中拉出且记录
post_sutdown 完成所有模拟阶段的未完事务。这一步的最后，会启动下一步也就是clean up stage

UVM driver

driver由uvm_driver继承而来，uvm_driver又是继承自uvm_component。

uvm_driver里的methods, TLM port等都是为了sequencer和driver之间的通信写的。uvm_driver是一个参数化的类，具体来说，是uvm_driver接收的sequence_item的类型（和发送的response 的类型，不过一般和接收的sequence_item一致）。

UVM driver methods

driver methods description
get_next_item 阻塞获取sequencer里面的下一个sequence_item
try_next_item 等同于非阻塞的get_next_item，如果没有可获取得sequence_item就会返回空指针
item_done 非阻塞地完成一次driver-sequencer握手，应该用在get_next_item或者是成功的try_next_item
put 非阻塞地将rsp送给sequencer

write code

  1. 继承 uvm_driver 基类

Driver 负责从 Sequencer 获取 Transaction 并将其驱动到物理总线上。

1
2
3
4
5
6
7
8
9
10
class mem_driver extends uvm_driver #(mem_seq_item);
    `uvm_component_utils(mem_driver)

    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction : new

endclass : mem_driver

  1. declare Virtual Interface

为了操作总线信号，需要声明一个虚接口句柄，并建议配合 clocking block 使用以避免竞争。

1
2
3
4
5
// declare virtual interface
virtual mem_if vif;

// 为了简化代码，通常在类外部或内部定义宏来指向 Clocking Block
`define DRIV_IF vif.DRIVER.driver_cb
  1. 通过 get 方法实现接口连接

在 build_phase 中，从 uvm_config_db 获取 Top 层传递的实际物理接口实例。

1
2
3
4
5
6
7

function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif)) begin
`uvm_fatal("NO_VIF", {"virtual interface must be set for: ", get_full_name(), ".vif"});
end
endfunction : build_phase
  1. 实现运行逻辑 (Run Phase)

在 run_phase 中通过 seq_item_port 与 Sequencer 握手，循环获取请求。

1
2
3
4
5
6
7
virtual task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
drive();
seq_item_port.item_done();
end
endtask : run_phase
  1. 实现驱动时序逻辑 (Drive Task)

将 Transaction 中的抽象数据转化为符合时序要求的时钟边沿信号。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
virtual task drive();
`DRIV_IF.wr_en <= 0;
    `DRIV_IF.rd_en <= 0;

    @(posedge vif.DRIVER.clk);
    `DRIV_IF.addr <= req.addr;

    if(req.wr_en) begin
        `DRIV_IF.wr_en <= req.wr_en;
        `DRIV_IF.wdata <= req.wdata;
        @(posedge vif.DRIVER.clk);
    end

    if(req.rd_en) begin
        `DRIV_IF.rd_en <= req.rd_en;
        @(posedge vif.DRIVER.clk);
        `DRIV_IF.rd_en <= 0;
        @(posedge vif.DRIVER.clk);
        req.rdata = `DRIV_IF.rdata;
    end

    $display("------------------------------------------------");

endtask : drive

UVM monitor

我们使用的monitor扩展自uvm_monitor，uvm_monitor又是继承自uvm_component.

monitor被动地通过虚接口从DUT获取信号，同时将signal信号级的活动转化为transcation事务级。monitor需要分配分析端口(TLM port)和指向DUT被测信号的interface handle.

write code

  1. extend uvm_monitor:
1
2
3
4
5
6
7
8
9
10
class mem_monitor extends uvm_monitor;
    `uvm_component_utils(mem_monitor)

    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
        trans_collected=new();
        item_collected_port=new("item_collected_port",this);
    endfunction:new
endclass:mem_monitor
  1. declare virtual interface
1
2
//virtual interface
virtual mem_if vif;
  1. 通过get method实现interface和virutal interface的连接
1
2
3
4
5
function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif))
        `uvm_fatal("NOVIF",{"virtual interface must be set for:",get_full_name(),".vif"});
endfunction:build_phase
  1. declare analysis port
1
uvm_analysis_port#(mem_seq_item)item_collected_port;
  1. declare seq_item handle
1
mem_seq_item trans_collected;
  1. add sampling logic in run_phase, and send the sampled transcation packet to scoreboard.
1
2
3
virtual task run_phase(uvm_phase phase);
    item_collected_port.write(trans_collected);
endtask:run_phase

完整代码如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
class mem_monitor extends uvm_monitor;

  // Virtual Interface
  virtual mem_if vif;

  uvm_analysis_port #(mem_seq_item) item_collected_port;

  // Placeholder to capture transaction information.
  mem_seq_item trans_collected;

  `uvm_component_utils(mem_monitor)

  // new - constructor
  function new (string name, uvm_component parent);
    super.new(name, parent);
    trans_collected = new();
    item_collected_port = new("item_collected_port", this);
  endfunction : new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif))
       `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"});
  endfunction: build_phase

  // run phase
  virtual task run_phase(uvm_phase phase);
    item_collected_port.write(trans_collected);
  endtask : run_phase

endclass : mem_monitor

UVM agent

我们定义的agent扩展自uvm_agent，uvm_agent又是继承自uvm_component.

一个典型的agent可以包括driver, sequencer, monitor，并且可以被配置为主动或者被动的。

active agent & passive agent

主动agent会产生激励并且驱动DUT，被动的agent只会从DUT采集信号而不能驱动信号，只由monitor组成。

一般默认的agent是主动的，如果需要设置，可以使以下方法:

1
2
3
set_config_int("path_to_agent", "is_active", UVM_ACTIVE);

set_config_int("path_to_agent", "is_active", UVM_PASSIVE);

如果想要知道agent是active还是passive，可以使用get_is_active()，会返回UVM_ACTIVE或者UVM_PASSIVE.

write code

  1. extend UVM_agent
1
2
3
4
5
6
7
8
9
10
class mem_agent extends uvm_agent;
    //UVM automatic macros for general components
    `uvm_component_utils(mem_agent)

    //constructor
        function new(string name, uvm_component parent);
            super.new(name, parent);
        endfunction:new

endclass:mem_agent
  1. declare driver, sequencer, monitor
1
2
3
mem_driver driver;
mem_sequencer sequencer;
mem_monitor monitor;
  1. create agent components in build phase(depending on agent type)
1
2
3
4
5
6
7
8
9
10
11
12
//build phase
function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    if(get_is_active() == UVM_ACTIVE) begin
        driver=mem_driver::type_id::create("driver",this);
        sequencer=mem_sequencer::typename::create("sequencer",this);

    end
    monitor=mem_monitor::type_id::create("monitor",this);
endfunction:build_phase

  1. driver的seq_item_port连接到sequencer的seq_item_export
1
2
3
4
5
6
7
//connect_phase

function void connect_phase(uvm_phase, phase);
    if(get_is_active() == UVM_ACTIVE)begin
        driver.seq_item_port.connect(sequencer.seq_item_export);
    end
endfunction:connect_phase

完整代码如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
class mem_agent extends uvm_agent;
  //declaring agent components
  mem_driver    driver;
  mem_sequencer sequencer;
  mem_monitor   monitor;

  // UVM automation macros for general components
  `uvm_component_utils(mem_agent)

  // constructor
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new

  // build_phase
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    if(get_is_active() == UVM_ACTIVE) begin
      driver = mem_driver::type_id::create("driver", this);
      sequencer = mem_sequencer::type_id::create("sequencer", this);
    end

    monitor = mem_monitor::type_id::create("monitor", this);
  endfunction : build_phase

  // connect_phase
  function void connect_phase(uvm_phase phase);
    if(get_is_active() == UVM_ACTIVE) begin
      driver.seq_item_port.connect(sequencer.seq_item_export);
    end
  endfunction : connect_phase

endclass : mem_agent

UVM scoreboard

uvm_component -> uvm_scoreboard.

write code:

  1. extend uvm_scoreboard
1
2
3
4
5
6
7
8
class mem_scoreboard extends uvm_scoreboard;
    `uvm_component_utils(mem_scoreboard)

    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction:new
endclass:mem_scoreboard

scoreboard会通过TLM port从monitor获取并且自动检测DUT的输出结果是否正确。

golden reference:预先写好的预期输入;
generated from reference model:参考模型生成的最终结果。

  1. declare & create TLM analysis port
1
2
3
4
5
//declare port
uvm_analysis_imp#(mem_seq_item, mem_scoreboard) item_collected_port;

//creating port
item_collected_port=new("item_collected_port", this);
  1. analysis export of scoreboard connect to monitor port
1
monitor.item_collected_port.connect(scoreboard.item_collected_port);
  1. scoreboard write function

scoreboard在调用write method的时候会从monitor获取transcation packet.

1
2
3
4
5
6
7
//calling write method from monitor
item_collected_port.write(pkt);

//scoreboard write function
virtual function void write(mem_seq_item pkt);
    pkt.print();
endfunction:write

完整代码如下:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
class mem_scoreboard extends uvm_scoreboard;

  `uvm_component_utils(mem_scoreboard)
  uvm_analysis_imp#(mem_seq_item, mem_scoreboard) item_collected_export;

  // new - constructor
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    item_collected_export = new("item_collected_export", this);
  endfunction: build_phase

  // write
  virtual function void write(mem_seq_item pkt);
    $display("SCB:: Pkt recived");
    pkt.print();
  endfunction : write

endclass : mem_scoreboard

UVM env

uvm_component -> uvm_env.

env作为一个container component，他里面会包含多个agents, 也可以用来作为scoreboard, top-level monitor, checker等的container.

write code

  1. extend from uvm_env.
1
2
3
4
5
6
7
8
class mem_model_env extends uvm_env;
    `uvm_component_utils(mem_model_env)

    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction:new
endclass:mem_model_env
  1. declare agent
1
mem_agent mem_agnt;
  1. create an agent.
1
mem_agnt=mem_agent::type_id::create("mem_agnt",this);

完整代码如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

class mem_model_env extends uvm_env;

  mem_agent mem_agnt;

  `uvm_component_utils(mem_model_env)

  // new - constructor
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new

  // build_phase
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    mem_agnt = mem_agent::type_id::create("mem_agnt", this);
  endfunction : build_phase

endclass : mem_model_env

UVM test

uvm_component -> uvm_test.

test用于设定“测试场景”。test设定了不同的测试场景，可以一次进行多次不同的测试。test contains environment, configuration properties, 还有class overrides.

UVM testbench在run_test()被调用之后正式开始。

1
2
3
initial begin
    run_test();
end

可执行的testcase可能是很多人一块写的，那么我们就需要一个选择testcase来运行的方法。有以下两个:

  1. run_test()里加入选择testcase的参数，如run_test("mem_model_test");
  2. 在开始仿真的命令里面加上：+UVM_TESTNAME=mem_model_test.

write code

  1. extend from uvm_test
1
2
3
4
5
6
7
8
class mem_model_test extends uvm_test;
    `uvm_component_utils(mem_model_test)

    function new(string name="mem_model_test", uvm_component parent=null);
        super.new(name, parent);
    endfunction:new

endclass:mem_model_test
  1. declare env & sequence
1
2
mem_model_env env;
mem_sequence seq;
  1. create env & sequence
1
2
env = mem_model_env::type_id::create("env", this);
seq=mem_sequence::type_id::create("seq");
  1. start sequence
1
seq.start(env.mem_agnt.sequencer);

完整代码如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
class mem_model_test extends uvm_test;
    `uvm_component_utils(mem_model_test)

    mem_model_env env;
    mem_sequence seq;

    function new(string name="mem_model_test", uvm_component=null);
        super.new(name, parent);
    endfunction:new

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        env=mem_model_env::type_id::create("env",this);
        seq=mem_sequence::type_id::create("seq");
    endfunction:build_phase

    task run_phase(uvm_phase phase);
        seq.start(env.mem_agnt.sequencer);
    endtask:run_phase
endclass:mem_model_test

UVM tb top

testbench top连接DUT和验证环境的所有组件。典型的tb top包括：

  • DUT instance
  • interface instance
  • run_test()
  • virtual interface set config_db
  • clock and reset generate logic
  • wave dump logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
module tbench_top;
    //clock and reset signal
    bit clk, reset;

    //clock generation
    always #5 clk=~clk;

    //reset generation
    initial begin
        reset=1;
        #5 reset=0;
    end

    //creating instance of interface, inorder to connect DUT and testcase
    mem_if intf(clk, reset);

    //DUT instance, interface connected to DUT ports;
    memory DUT(.clk(intf.clk), .reset(intf.reset), .addr(intf.addr),
                .wr_en(intf.wr_en), .rd_en(intf.rd_en), .wdata(intf.wdata),
                .rdata(intf.rdata));

    //enabling the wave dump
    initial begin
        uvm_config_db#(virtual mem_if)::set(uvm_root::get(), "*", "mem_intf",intf);
        $dumpfile("dump.vcd");
        $dumpvars;
    end

    initial begin
        run_test();
    end
endmodule

测试设计流程

相关代码资源等来自:UVM TestBench, EDA playground

我们现在需要完成一个内存模型的测试流程，内存模型的设计代码如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

//------------------------------------------------------------------------
//  Memory Model RTL - www.verificationguide.com
//------------------------------------------------------------------------
/*
              -----------------
              |               |
    addr ---->|               |
              |               |------> rdata
              | Memory Model  |
   wdata ---->|               |
              |               |
              -----------------
                   ^     ^
                   |     |
                wr_en  rd_en

-------------------------------------------------------------------------- */
module memory
  #( parameter ADDR_WIDTH = 4,
     parameter DATA_WIDTH = 8 ) (
    input clk,
    input reset,

    //control signals
    input [ADDR_WIDTH-1:0]  addr,
    input                   wr_en,
    input                   rd_en,

    //data signals
    input  [DATA_WIDTH-1:0] wdata,
    output logic [DATA_WIDTH-1:0] rdata
  );

  //reg [DATA_WIDTH-1:0] rdata;

  //Memory
  reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH];

  //Reset
  always @(posedge reset)
    for(int i=0;i<2**ADDR_WIDTH;i++) mem[i]=8'hFF;

  // Write data to Memory
  always @(posedge clk)
    if (wr_en)    mem[addr] <= wdata;

  // Read data from memory
  always @(posedge clk)
    if (rd_en) rdata <= mem[addr];

endmodule

这个模块实现了一个基本的读写功能。内存模块共有四个地址，用两位(ADDR_WIDTH)表示，每个地址对应的空间大小是8位(DATA_WIDTH). 当reset信号被拉高，就会把内存中所有数据清空(置为8’hFF)，否则，在时钟上升沿检测wr_en/rd_en，如有使能信号为高，则对addr输入地址内的空间执行对应操作。

要如何进行对这个设计文件的测试呢？

通常代码的编写顺序是从底层到高层，如果需要对已经写过的代码验证，就受到编译依赖的限制，所以一般是：

interface -> sequence-item -> sequence -> agent components(sequencer + driver + config-db)
-> env -> test -> top

interface

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
interface mem_if(input logic clk, reset);

    logic [3:0] addr;
    logic wr_en;
    logic rd_en;
    logic [7:0] wdata;
    logic [7:0] rdata;

    clocking driver_cb @(posedge clk);
        default input #1 output #1;
        output addr;
        output wr_en;
        output rd_en;
        output wdata;
        input rdata;
    endclocking


    clocking monitor_cb @(posedge clk);
        default input #1 output #1;
        input addr;
        input wr_en;
        input rd_en;
        input wdata;
        input rdata;
    endclocking

    modport DRIVER(clocking driver_cb, input clk, reset);
    modport MONITOR(clocking monitor_cb, input clk, reset);
endinterface

sequence-item

我们已经知道了sequence-item是信息交流的基石，他是DUT和验证平台之间的最小信息单元，所以需要先写sequence-item.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
import uvm_pkg::*;
`include "uvm_macros.svh"

class mem_seq_item extends uvm_sequence_item;

    //data and control fields.
    rand bit [3:0] addr;
    rand bit wr_en;
    rand bit rd_en;
    rand bit [7:0] wdata;
    rand bit [7:0] rdata;
    // rand for randomize.

    //utility and field macros.
    `uvm_object_utils_begin(mem_seq_item)
        `uvm_field_int(addr, UVM_ALL_ON)
        `uvm_field_int(wr_en, UVM_ALL_ON)
        `uvm_field_int(rd_en, UVM_ALL_ON)
        `uvm_field_int(wdata, UVM_ALL_ON)
    `uvm_object_utils_end


    //constructor
    function new(string name="mem_seq_item");
        super.new(name);
    endfunction

    //constraints.
    constraint wr_rd_c {wr_en != rd_en;};
endclass

sequence

sequence产生随机的数据流。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
typedef class mem_sequencer;
class mem_sequence extends uvm_sequence#(mem_seq_item);
    `uvm_object_utils(mem_sequence)

    //constructor
    function new(string name="mem_sequence");
        super.new(name);
    endfunction

    //body method: generate and send seq_item.
    virtual task body();
        req=mem_seq_item::type_id::create("req");
        wait_for_grant();
        req.randomize();
        send_request(req);
        wait_for_item_done();
    endtask
endclass


class mem_wr_seq extends uvm_sequence#(mem_seq_item);
    `uvm_object_utils(mem_wr_seq)

    //constructor
    function new(string name="mem_wr_seq");
        super.new(name);
    endfunction

    virtual task body();
        `uvm_do_with(req, {req.wr_en == 1;})
    endtask
endclass


class mem_rd_seq extends uvm_sequence#(mem_seq_item);
    `uvm_object_utils(mem_rd_seq)

    //constructor
    function new(string name ="mem_rd_seq");
        super.new(name);
    endfunction

    virtual task body();
        `uvm_do_with(req,{req.rd_en==1;})
    endtask
endclass
class mem_write_read_seq extends uvm_sequence#(mem_seq_item);
    `uvm_object_utils(mem_write_read_seq)

    function new(string name="mem_write_read_seq");
        super.new(name);
    endfunction

    virtual task body();
        // 1. 写一笔数据
        `uvm_do_with(req, {
            addr  == 4'hb;
            wr_en == 1;
            rd_en == 0;
            wdata == 8'h55;
        })

        // 2. 读同一地址
        `uvm_do_with(req, {
            addr  == 4'hb;
            wr_en == 0;
            rd_en == 1;
        })
    endtask
endclass

关于这里为什么写三个：mem_sequence是一个基础的序列，不指定具体读写而是简单的随机化，可以进行随机压力测试；mem_wr_seq专门进行写操作，mem_rd_seq专门进行读操作，分开之后可以进行可控的操作。

关于具体产生随机数据流的方式：这里已经展示了两种方式，第一种是mem_sequence中的写法，关键在于req.randomize(), 他会根据之前mem_seq_item中的rand属性标签和constraint的约束完成一次随机化；第二种方式是之后写的`uvm_do_with(req, {req.wr_en==1;})，自动完成上面的创建和随机化，with和{req.wr_en==1;}代表引入的约束。

sequencer

sequencer负责进行仲裁，决定流向driver的数据(或者是从driver流回)的顺序。

sequence和sequencer两者共同形成了推送sequence-item的动力源。

1
2
3
4
5
6
7
8
9

class mem_sequencer extends uvm_sequencer#(mem_seq_item);
    `uvm_component_utils(mem_sequencer)

    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction
endclass

driver

driver接收sequencer传来的激励信号并且基于接口信号驱动。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65

`define DRIV_IF vif.DRIVER.driver_cb
//不写这个的话每次赋值都要写一次vif.DRIVER.driver_cb
class mem_driver extends uvm_driver#(mem_seq_item);

    `uvm_component_utils(mem_driver)

    //virtual interface
    virtual mem_if vif;

    //uvm_analysis_port#(mem_seq_item) Drvr2Sb_port;


    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction:new

    function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        if(!uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif))
            `uvm_fatal("NO_VIF",{"virtual interface must be set for:",get_full_name(),".vif"});
    endfunction:build_phase


    //run_phase
    virtual task run_phase(uvm_phase phase);
        forever begin
            seq_item_port.get_next_item(req);
            //respond_to_transfer(req);
            drive();
            seq_item_port.item_done();
        end

endtask:run_phase
    //drive

    virtual task drive();
        req.print();
        `DRIV_IF.wr_en<=0;
        `DRIV_IF.rd_en<=0;
        @(posedge vif.DRIVER.clk)
        `DRIV_IF.addr<=req.addr;
        if(req.wr_en)begin
            `DRIV_IF.wr_en<=req.wr_en;
            `DRIV_IF.wdata<=req.wdata;
            //$display("\tADDR=%0h \tWDATA=%0h",req.addr,trans.wdata);
            @(posedge vif.DRIVER.clk);
        end

        if(req.rd_en)begin
            `DRIV_IF.rd_en<=req.rd_en;
            @(posedge vif.DRIVER.clk);
            `DRIV_IF.rd_en <= 0;
            @(posedge vif.DRIVER.clk);
            req.rdata=`DRIV_IF.rdata;
            //$display("\tADDR=%0h \tRDATA=%0h",trans.addr, `DRIV_IF.rdata);
        end
        $display("---------------------------------------------------");
    endtask:drive



endclass:mem_driver

monitor

monitor通过虚拟接口完成DUT信号采集，并且把signal-level活动转化为transcation-level.

driver & monitor是唯二可以接触virtual interface的组件。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
class mem_monitor extends uvm_monitor;
    `uvm_component_utils(mem_monitor)

    //virtual interface
    virtual mem_if vif;

    //declare analysis port.
    uvm_analysis_port#(mem_seq_item) item_collected_port;


    //Placeholder to capture transcation information
    mem_seq_item trans_collected;

    //constructor
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction:new

    //build_phase.
    //connect interface to virtual interface by using get method.
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        item_collected_port=new("item_collected_port", this);
        if(!uvm_config_db#(virtual mem_if)::get(this, "","vif",vif))
            `uvm_fatal("NO_VIF",{"virtual interface must be set for:",get_full_name(),".vif"});
    endfunction:build_phase

    //run phase
    virtual task run_phase(uvm_phase phase);
    forever begin
        // 1. 等待 clocking block 事件触发（相当于等待时钟上升沿且考虑了 skew）
        @(vif.monitor_cb);

        // 2. 在时钟沿检查使能信号，如果有效则开始处理
        if (vif.monitor_cb.wr_en || vif.monitor_cb.rd_en) begin

            // 实例化新的 transaction
            trans_collected = mem_seq_item::type_id::create("trans_collected");

            // 3. 立即采样地址，防止地址信号在下一个时钟改变
            trans_collected.addr = vif.monitor_cb.addr;

            if (vif.monitor_cb.wr_en) begin
                trans_collected.wr_en = 1;
                trans_collected.rd_en = 0;
                trans_collected.wdata = vif.monitor_cb.wdata;
                // 写操作通常在一个周期内采样完成
            end
            else if (vif.monitor_cb.rd_en) begin
                trans_collected.rd_en = 1;
                trans_collected.wr_en = 0;

                // 4. 处理读潜伏期 (Latency)
                // 如果 DUT 读数据需要 2 拍，则等待两拍采样数据
                repeat(2) @(vif.monitor_cb);
                trans_collected.rdata = vif.monitor_cb.rdata;
            end

            // 5. 发送数据
            `uvm_info("MON_DEBUG", $sformatf("Monitor write: addr=%0h, data=%0h", trans_collected.addr, trans_collected.rdata), UVM_LOW)
            item_collected_port.write(trans_collected);
        end
    end
endtask:run_phase
endclass:mem_monitor

agent

agent将driver, sequencer, monitor包装在一起，如果有多个内存接口只要实例化多个mem_agent, 可以实现代码复用.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

class mem_agent extends uvm_agent;
    //macros.
    `uvm_component_utils(mem_agent)

    //constructor.
    function new(string name, uvm_component parent);
        super.new(name,parent);
    endfunction:new

    //declare agent components.
    mem_driver driver;
    mem_sequencer sequencer;
    mem_monitor monitor;

    //build_phase
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        if(get_is_active() == UVM_ACTIVE)begin
            driver=mem_driver::type_id::create("driver",this);
            sequencer=mem_sequencer::type_id::create("sequencer", this);
        end

        monitor=mem_monitor::type_id::create("monitor", this);
    endfunction:build_phase

    //connect driver / sequencer
    function void connect_phase(uvm_phase phase);
        if(get_is_active() ==UVM_ACTIVE)begin
            driver.seq_item_port.connect(sequencer.seq_item_export);
        end
    endfunction:connect_phase

endclass:mem_agent

scoreboard

scoreboard接收monitor发来的transcation，同时和参考值进行对比。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
class mem_scoreboard extends uvm_scoreboard;
    `uvm_component_utils(mem_scoreboard)


    mem_seq_item pkt_qu[$];
    bit [7:0] sc_mem [16];

    //declare port.
    uvm_analysis_imp#(mem_seq_item, mem_scoreboard) item_collected_export;

    //constructor.
    function new (string name, uvm_component parent);
        super.new(name, parent);
    endfunction : new


    function void build_phase(uvm_phase phase);
    super.build_phase(phase);
      item_collected_export = new("item_collected_export", this);
      foreach(sc_mem[i]) sc_mem[i] = 8'hFF;
  endfunction: build_phase

    //write.
     virtual function void write(mem_seq_item pkt);
    //pkt.print();
    `uvm_info("SCB_DEBUG", "Data recived in scoreboard.",UVM_LOW)
    pkt_qu.push_back(pkt);
  endfunction : write

    // run phase
    virtual task run_phase(uvm_phase phase);
    //--------------compare logic-----------------------
        mem_seq_item mem_pkt;

        forever begin
            wait(pkt_qu.size() > 0);
            mem_pkt = pkt_qu.pop_front();

            if(mem_pkt.wr_en) begin
                    sc_mem[mem_pkt.addr] = mem_pkt.wdata;
                    `uvm_info(get_type_name(),$sformatf("------ :: WRITE DATA       :: ------"),UVM_LOW)
                    `uvm_info(get_type_name(),$sformatf("Addr: %0h",mem_pkt.addr),UVM_LOW)
                    `uvm_info(get_type_name(),$sformatf("Data: %0h",mem_pkt.wdata),UVM_LOW)
                    `uvm_info(get_type_name(),"------------------------------------",UVM_LOW)
            end
            else if(mem_pkt.rd_en) begin
                if(sc_mem[mem_pkt.addr] == mem_pkt.rdata) begin
                    `uvm_info(get_type_name(),$sformatf("------ :: READ DATA Match :: ------"),UVM_LOW)
                    `uvm_info(get_type_name(),$sformatf("Addr: %0h",mem_pkt.addr),UVM_LOW)
                    `uvm_info(get_type_name(),$sformatf("Expected Data: %0h Actual Data: %0h",sc_mem[mem_pkt.addr],mem_pkt.rdata),UVM_LOW)
                    `uvm_info(get_type_name(),"------------------------------------",UVM_LOW)
                end
                else begin
                `uvm_error(get_type_name(),"------ :: READ DATA MisMatch :: ------")
                `uvm_info(get_type_name(),$sformatf("Addr: %0h",mem_pkt.addr),UVM_LOW)
                `uvm_info(get_type_name(),$sformatf("Expected Data: %0h Actual Data: %0h",sc_mem[mem_pkt.addr],mem_pkt.rdata),UVM_LOW)
                `uvm_info(get_type_name(),"------------------------------------",UVM_LOW)
                end
            end
        end
    endtask : run_phase

endclass:mem_scoreboard

env

env可以包含多个agents，用来把以上组件串联起来。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
class mem_model_env extends uvm_env;
    mem_agent mem_agnt;
    mem_scoreboard mem_scb;

    `uvm_component_utils(mem_model_env)

    //constructor.
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction:new

    //build_phase.
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        mem_agnt=mem_agent::type_id::create("mem_agnt", this);
        mem_scb=mem_scoreboard::type_id::create("mem_scb",this);
    endfunction:build_phase

    //connect_phase.
    function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
        if (mem_agnt == null)
        `uvm_fatal("NOCONN", "mem_agnt is null!")
    if (mem_agnt.monitor == null)
        `uvm_fatal("NOCONN", "mem_agnt.monitor is null! Check build_phase in mem_agent.")
    if (mem_scb == null)
        `uvm_fatal("NOCONN", "mem_scb is null!")
        mem_agnt.monitor.item_collected_port.connect(mem_scb.item_collected_export);
    endfunction:connect_phase
endclass:mem_model_env

test

test为testbench启动测试提供不同的测试场景。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

class mem_model_test extends uvm_test;
    `uvm_component_utils(mem_model_test)

    mem_model_env env;
    mem_sequence seq;
    mem_write_read_seq wr_rd_seq;

    function new(string name="mem_model_test", uvm_component parent=null);
        super.new(name, parent);
    endfunction:new

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        env=mem_model_env::type_id::create("env",this);
        //seq=mem_sequence::type_id::create("seq");
        wr_rd_seq=mem_write_read_seq::type_id::create("wr_rd_seq");
    endfunction:build_phase

    task run_phase(uvm_phase phase);
        phase.raise_objection(this);
        wr_rd_seq.start(env.mem_agnt.sequencer);
	#100
        phase.drop_objection(this);
    endtask:run_phase
endclass:mem_model_test

phase.raise_objection(this)和phase.drop_objection(this)的作用是：因为一定是先进入run_phase这个任务，才发出信号seq.start(env.mem_agnt.sequencer)，让sequence给sequencer发req，但是进入任务之后，发出信号之前，仿真器发现无事可做就会直接退出，最后啥也没运行。所以这一组命令的作用就是，raise代表告诉仿真器我还有活要整，drop表示我没活了，这样才能正确运行。

tb_top

tb_top相当于开始仿真的总开关。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

module tbench_top;
    //clock & reset.
    bit clk;
    bit reset;

    //clock generation.
    always #5 clk=~clk;

    //reset generation.
    initial begin
        reset=1;
        #5 reset=0;
    end

    //create instance.
    mem_if intf(clk, reset);

    //DUT instance.
    memory DUT(
    .clk(intf.clk),
    .reset(intf.reset),
    .addr(intf.addr),
    .wr_en(intf.wr_en),
    .rd_en(intf.rd_en),
    .wdata(intf.wdata),
    .rdata(intf.rdata)
    );

    //enable wave dump.
    initial begin
        uvm_config_db#(virtual mem_if)::set(uvm_root::get(),"*","vif",intf);
        $dumpfile("dump.vcd");
        $dumpvars;
    end

    initial begin
    run_test();
    end
endmodule

run!!!

也是终于到这一步了喵！辛苦各位喵！

写下运行脚本：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

vcs -full64 -sverilog -ntb_opts uvm-1.2 \
	interface.sv \
	memory.sv \
	sequence_item.sv \
	sequencer.sv \
	sequence.sv \
	driver.sv \
	monitor.sv \
	agent.sv \
	scoreboard.sv \
	env.sv \
	test.sv \
	tb_top.sv \
	-debug_access+all > compile.log
./simv +UVM_TESTNAME=mem_model_test > result.log

最终结果是：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
                         Chronologic VCS (TM)
       Version O-2018.09-SP2_Full64 -- Sun Jan 18 01:06:15 2026
               Copyright (c) 1991-2018 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_pkg.sv'
Parsing included file '/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
...
...
...
recompiling module uvm_custom_install_recording
recompiling module uvm_custom_install_verdi_recording
recompiling module tbench_top
5 of 9 modules done
	However, due to incremental compilation, only 5 modules need to be compiled.
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared  -Bsymbolic  -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o
rm -f _csrc0.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -rdynamic  -Wl,-rpath=/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib -L/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib  uvm_dpi.o uvm_verdi_dpi.o     _23371_archive_1.so _prev_archive_1.so _csrc0.so  SIM_l.o  _csrc0.so    rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive       ./../simv.daidir/vc_hdrs.o  _vcs_pli_stub_.o   /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o /opt/Synopsys/Verdi2018/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl
../simv up to date
CPU time: 7.380 seconds to compile + .231 seconds to elab + .335 seconds to link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 18 01:06 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES] 
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test mem_model_test...
------------------------------------------------------------------------------------------------
Name                           Type          Size  Value                                        
------------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @604                                         
  addr                         integral      4     'hb                                          
  wr_en                        integral      1     'h1                                          
  rd_en                        integral      1     'h0                                          
  wdata                        integral      8     'h55                                         
  begin_time                   time          64    0                                            
  depth                        int           32    'd2                                          
  parent sequence (name)       string        9     wr_rd_seq                                    
  parent sequence (full name)  string        45    uvm_test_top.env.mem_agnt.sequencer.wr_rd_seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer          
------------------------------------------------------------------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------------
Name                           Type          Size  Value                                        
------------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @634                                         
  addr                         integral      4     'hb                                          
  wr_en                        integral      1     'h0                                          
  rd_en                        integral      1     'h1                                          
  wdata                        integral      8     'h8a                                         
  begin_time                   time          64    15                                           
  depth                        int           32    'd2                                          
  parent sequence (name)       string        9     wr_rd_seq                                    
  parent sequence (full name)  string        45    uvm_test_top.env.mem_agnt.sequencer.wr_rd_seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer          
------------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 15: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=b, data=0
UVM_INFO scoreboard.sv(26) @ 15: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: b
UVM_INFO scoreboard.sv(43) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 55
UVM_INFO scoreboard.sv(44) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
UVM_INFO monitor.sv(60) @ 55: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=b, data=55
UVM_INFO scoreboard.sv(26) @ 55: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: b
UVM_INFO scoreboard.sv(50) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 55 Actual Data: 55
UVM_INFO scoreboard.sv(51) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_objection.svh(1276) @ 145: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_catcher.svh(705) @ 145: reporter [UVM/REPORT/CATCHER] 
--- UVM Report catcher Summary ---


Number of demoted UVM_FATAL reports  :    0
Number of demoted UVM_ERROR reports  :    0
Number of demoted UVM_WARNING reports:    0
Number of caught UVM_FATAL reports   :    0
Number of caught UVM_ERROR reports   :    0
Number of caught UVM_WARNING reports :    0

UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_server.svh(894) @ 145: reporter [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   16
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[MON_DEBUG]     2
[RNTST]     1
[SCB_DEBUG]     2
[TEST_DONE]     1
[UVM/RELNOTES]     1
[UVM/REPORT/CATCHER]     1
[mem_scoreboard]     8

$finish called from file "/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh", line 527.
$finish at simulation time                  145
           V C S   S i m u l a t i o n   R e p o r t 
Time: 145
CPU Time:      0.290 seconds;       Data structure size:   0.5Mb
Sun Jan 18 01:06:24 2026

结果说明，15ns向0xb写数据0x55，55ns从0xb读出了0x55，功能基本正常。

如果我们需要多次测试可以怎么写呢？

首先是可以多写几个测试类，比如我们在test.sv里面加一条：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

class mem_model_test2 extends uvm_test;
    `uvm_component_utils(mem_model_test2)

    mem_model_env env;
    mem_sequence seq;

    function new(string name="mem_model_test2", uvm_component parent=null);
        super.new(name, parent);
    endfunction:new

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        env=mem_model_env::type_id::create("env",this);
        //seq=mem_sequence::type_id::create("seq");
        seq=mem_sequence::type_id::create("seq");
    endfunction:build_phase

    task run_phase(uvm_phase phase);
        phase.raise_objection(this);
        seq.start(env.mem_agnt.sequencer);
	#100
        phase.drop_objection(this);
    endtask:run_phase
endclass:mem_model_test2

在run.sh最后加一句：

1
./simv +UVM_TESTNAME=mem_model_test2 >> result2.log

我们所得到的结果就是：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 18 13:02 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test mem_model_test...
------------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @604
  addr                         integral      4     'hb
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h55
  begin_time                   time          64    0
  depth                        int           32    'd2
  parent sequence (name)       string        9     wr_rd_seq
  parent sequence (full name)  string        45    uvm_test_top.env.mem_agnt.sequencer.wr_rd_seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @634
  addr                         integral      4     'hb
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h8a
  begin_time                   time          64    15
  depth                        int           32    'd2
  parent sequence (name)       string        9     wr_rd_seq
  parent sequence (full name)  string        45    uvm_test_top.env.mem_agnt.sequencer.wr_rd_seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 15: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=b, data=0
UVM_INFO scoreboard.sv(26) @ 15: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: b
UVM_INFO scoreboard.sv(43) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 55
UVM_INFO scoreboard.sv(44) @ 15: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
UVM_INFO monitor.sv(60) @ 55: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=b, data=55
UVM_INFO scoreboard.sv(26) @ 55: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: b
UVM_INFO scoreboard.sv(50) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 55 Actual Data: 55
UVM_INFO scoreboard.sv(51) @ 55: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_objection.svh(1276) @ 145: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_catcher.svh(705) @ 145: reporter [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---


Number of demoted UVM_FATAL reports  :    0
Number of demoted UVM_ERROR reports  :    0
Number of demoted UVM_WARNING reports:    0
Number of caught UVM_FATAL reports   :    0
Number of caught UVM_ERROR reports   :    0
Number of caught UVM_WARNING reports :    0

UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_server.svh(894) @ 145: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   16
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[MON_DEBUG]     2
[RNTST]     1
[SCB_DEBUG]     2
[TEST_DONE]     1
[UVM/RELNOTES]     1
[UVM/REPORT/CATCHER]     1
[mem_scoreboard]     8

$finish called from file "/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh", line 527.
$finish at simulation time                  145
           V C S   S i m u l a t i o n   R e p o r t
Time: 145
CPU Time:      0.350 seconds;       Data structure size:   0.5Mb
Sun Jan 18 13:02:50 2026
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 18 13:02 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test mem_model_test2...
----------------------------------
Name     Type          Size  Value
----------------------------------
req      mem_seq_item  -     @604
  addr   integral      4     'hb
  wr_en  integral      1     'h0
  rd_en  integral      1     'h1
  wdata  integral      8     'h19
----------------------------------
---------------------------------------------------
UVM_INFO monitor.sv(60) @ 35: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=b, data=ff
UVM_INFO scoreboard.sv(26) @ 35: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: b
UVM_INFO scoreboard.sv(50) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_objection.svh(1276) @ 125: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_catcher.svh(705) @ 125: reporter [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---


Number of demoted UVM_FATAL reports  :    0
Number of demoted UVM_ERROR reports  :    0
Number of demoted UVM_WARNING reports:    0
Number of caught UVM_FATAL reports   :    0
Number of caught UVM_ERROR reports   :    0
Number of caught UVM_WARNING reports :    0

UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_server.svh(894) @ 125: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   10
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[MON_DEBUG]     1
[RNTST]     1
[SCB_DEBUG]     1
[TEST_DONE]     1
[UVM/RELNOTES]     1
[UVM/REPORT/CATCHER]     1
[mem_scoreboard]     4

$finish called from file "/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh", line 527.
$finish at simulation time                  125
           V C S   S i m u l a t i o n   R e p o r t
Time: 125
CPU Time:      0.280 seconds;       Data structure size:   0.5Mb
Sun Jan 18 13:02:50 2026

第二种方法是用repeat进行多次操作。比如说我要进行多次写后读，可以修改sequence.sv的task body的定义，或者重写一个。

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
class mem_random_w_r extends uvm_sequence#(mem_seq_item);
    `uvm_object_utils(mem_random_w_r)

    //constructor
    function new(string name="mem_random_w_r");
        super.new(name);
    endfunction

    //body method: generate and send seq_item.
    virtual task body();
        repeat(20) begin
            bit [3:0] temp_addr;
            temp_addr =$urandom_range(0,15);
            `uvm_do_with(req, {rd_en==1; addr==temp_addr;})
            `uvm_do_with(req, {wr_en==1; addr==temp_addr;})
            `uvm_do_with(req, {rd_en==1; addr==temp_addr;})
        end
    endtask
endclass

这里定义了一个对于同一地址的多次r-w-r操作，之后我们再去修改test.sv应用这个测试：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
class mem_model_test3 extends uvm_test;
    `uvm_component_utils(mem_model_test3)

    mem_model_env env;
    mem_random_w_r seq;

    function new(string name="mem_model_test3", uvm_component parent=null);
        super.new(name, parent);
    endfunction:new

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        env=mem_model_env::type_id::create("env",this);
        //seq=mem_sequence::type_id::create("seq");
        seq=mem_random_w_r::type_id::create("seq");
    endfunction:build_phase

    task run_phase(uvm_phase phase);
        phase.raise_objection(this);
        seq.start(env.mem_agnt.sequencer);
	#100
        phase.drop_objection(this);
    endtask:run_phase
endclass:mem_model_test3

之后修改run.sh：

1
./simv +UVM_TESTNAME=mem_model_test3 > result.log

运行结果如下：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Jan 18 13:27 2026
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test mem_model_test3...
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @604
  addr                         integral      4     'h2
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h1f
  begin_time                   time          64    0
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @638
  addr                         integral      4     'h2
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h67
  begin_time                   time          64    25
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 35: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=2, data=ff
UVM_INFO scoreboard.sv(26) @ 35: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 2
UVM_INFO scoreboard.sv(50) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 35: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @654
  addr                         integral      4     'h2
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h8d
  begin_time                   time          64    45
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 45: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=2, data=0
UVM_INFO scoreboard.sv(26) @ 45: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 45: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 45: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 2
UVM_INFO scoreboard.sv(43) @ 45: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 67
UVM_INFO scoreboard.sv(44) @ 45: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @678
  addr                         integral      4     'ha
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h8d
  begin_time                   time          64    75
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 85: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=2, data=67
UVM_INFO scoreboard.sv(26) @ 85: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 85: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 85: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 2
UVM_INFO scoreboard.sv(50) @ 85: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 67 Actual Data: 67
UVM_INFO scoreboard.sv(51) @ 85: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @698
  addr                         integral      4     'ha
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hce
  begin_time                   time          64    105
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 115: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=a, data=ff
UVM_INFO scoreboard.sv(26) @ 115: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 115: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 115: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: a
UVM_INFO scoreboard.sv(50) @ 115: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 115: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @714
  addr                         integral      4     'ha
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hb5
  begin_time                   time          64    125
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 125: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=a, data=0
UVM_INFO scoreboard.sv(26) @ 125: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 125: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 125: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: a
UVM_INFO scoreboard.sv(43) @ 125: uvm_test_top.env.mem_scb [mem_scoreboard] Data: ce
UVM_INFO scoreboard.sv(44) @ 125: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @738
  addr                         integral      4     'h9
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h78
  begin_time                   time          64    155
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 165: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=a, data=ce
UVM_INFO scoreboard.sv(26) @ 165: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 165: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 165: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: a
UVM_INFO scoreboard.sv(50) @ 165: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ce Actual Data: ce
UVM_INFO scoreboard.sv(51) @ 165: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @758
  addr                         integral      4     'h9
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h96
  begin_time                   time          64    185
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 195: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=9, data=ff
UVM_INFO scoreboard.sv(26) @ 195: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 195: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 195: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 9
UVM_INFO scoreboard.sv(50) @ 195: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 195: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @774
  addr                         integral      4     'h9
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h94
  begin_time                   time          64    205
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 205: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=9, data=0
UVM_INFO scoreboard.sv(26) @ 205: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 205: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 205: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 9
UVM_INFO scoreboard.sv(43) @ 205: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 96
UVM_INFO scoreboard.sv(44) @ 205: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @798
  addr                         integral      4     'he
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h47
  begin_time                   time          64    235
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 245: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=9, data=96
UVM_INFO scoreboard.sv(26) @ 245: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 245: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 245: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 9
UVM_INFO scoreboard.sv(50) @ 245: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 96 Actual Data: 96
UVM_INFO scoreboard.sv(51) @ 245: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @818
  addr                         integral      4     'he
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'he0
  begin_time                   time          64    265
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 275: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=e, data=ff
UVM_INFO scoreboard.sv(26) @ 275: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 275: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 275: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: e
UVM_INFO scoreboard.sv(50) @ 275: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 275: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @834
  addr                         integral      4     'he
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hcc
  begin_time                   time          64    285
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 285: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=e, data=0
UVM_INFO scoreboard.sv(26) @ 285: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 285: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 285: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: e
UVM_INFO scoreboard.sv(43) @ 285: uvm_test_top.env.mem_scb [mem_scoreboard] Data: e0
UVM_INFO scoreboard.sv(44) @ 285: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @858
  addr                         integral      4     'h7
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hee
  begin_time                   time          64    315
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 325: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=e, data=e0
UVM_INFO scoreboard.sv(26) @ 325: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 325: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 325: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: e
UVM_INFO scoreboard.sv(50) @ 325: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: e0 Actual Data: e0
UVM_INFO scoreboard.sv(51) @ 325: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @878
  addr                         integral      4     'h7
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hd3
  begin_time                   time          64    345
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 355: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=7, data=ff
UVM_INFO scoreboard.sv(26) @ 355: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 355: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 355: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 7
UVM_INFO scoreboard.sv(50) @ 355: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 355: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @894
  addr                         integral      4     'h7
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hd6
  begin_time                   time          64    365
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 365: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=7, data=0
UVM_INFO scoreboard.sv(26) @ 365: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 365: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 365: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 7
UVM_INFO scoreboard.sv(43) @ 365: uvm_test_top.env.mem_scb [mem_scoreboard] Data: d3
UVM_INFO scoreboard.sv(44) @ 365: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @918
  addr                         integral      4     'h7
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h82
  begin_time                   time          64    395
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 405: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=7, data=d3
UVM_INFO scoreboard.sv(26) @ 405: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 405: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 405: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 7
UVM_INFO scoreboard.sv(50) @ 405: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: d3 Actual Data: d3
UVM_INFO scoreboard.sv(51) @ 405: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @938
  addr                         integral      4     'h7
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h93
  begin_time                   time          64    425
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 435: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=7, data=d3
UVM_INFO scoreboard.sv(26) @ 435: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 435: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 435: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 7
UVM_INFO scoreboard.sv(50) @ 435: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: d3 Actual Data: d3
UVM_INFO scoreboard.sv(51) @ 435: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @954
  addr                         integral      4     'h7
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h21
  begin_time                   time          64    445
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 445: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=7, data=0
UVM_INFO scoreboard.sv(26) @ 445: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 445: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 445: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 7
UVM_INFO scoreboard.sv(43) @ 445: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 93
UVM_INFO scoreboard.sv(44) @ 445: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @978
  addr                         integral      4     'h8
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h84
  begin_time                   time          64    475
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 485: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=7, data=93
UVM_INFO scoreboard.sv(26) @ 485: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 485: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 485: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 7
UVM_INFO scoreboard.sv(50) @ 485: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 93 Actual Data: 93
UVM_INFO scoreboard.sv(51) @ 485: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @998
  addr                         integral      4     'h8
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hf6
  begin_time                   time          64    505
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 515: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=8, data=ff
UVM_INFO scoreboard.sv(26) @ 515: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 515: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 515: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 8
UVM_INFO scoreboard.sv(50) @ 515: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 515: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1014
  addr                         integral      4     'h8
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hb5
  begin_time                   time          64    525
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 525: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=8, data=0
UVM_INFO scoreboard.sv(26) @ 525: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 525: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 525: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 8
UVM_INFO scoreboard.sv(43) @ 525: uvm_test_top.env.mem_scb [mem_scoreboard] Data: f6
UVM_INFO scoreboard.sv(44) @ 525: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1038
  addr                         integral      4     'h0
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h7f
  begin_time                   time          64    555
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 565: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=8, data=f6
UVM_INFO scoreboard.sv(26) @ 565: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 565: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 565: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 8
UVM_INFO scoreboard.sv(50) @ 565: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: f6 Actual Data: f6
UVM_INFO scoreboard.sv(51) @ 565: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1058
  addr                         integral      4     'h0
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h14
  begin_time                   time          64    585
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 595: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=0, data=ff
UVM_INFO scoreboard.sv(26) @ 595: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 595: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 595: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 0
UVM_INFO scoreboard.sv(50) @ 595: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 595: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1074
  addr                         integral      4     'h0
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h60
  begin_time                   time          64    605
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 605: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=0, data=0
UVM_INFO scoreboard.sv(26) @ 605: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 605: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 605: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 0
UVM_INFO scoreboard.sv(43) @ 605: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 14
UVM_INFO scoreboard.sv(44) @ 605: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1098
  addr                         integral      4     'hd
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h6f
  begin_time                   time          64    635
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 645: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=0, data=14
UVM_INFO scoreboard.sv(26) @ 645: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 645: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 645: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 0
UVM_INFO scoreboard.sv(50) @ 645: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 14 Actual Data: 14
UVM_INFO scoreboard.sv(51) @ 645: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1118
  addr                         integral      4     'hd
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'ha1
  begin_time                   time          64    665
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 675: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=d, data=ff
UVM_INFO scoreboard.sv(26) @ 675: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 675: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 675: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: d
UVM_INFO scoreboard.sv(50) @ 675: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 675: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1134
  addr                         integral      4     'hd
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h60
  begin_time                   time          64    685
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 685: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=d, data=0
UVM_INFO scoreboard.sv(26) @ 685: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 685: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 685: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: d
UVM_INFO scoreboard.sv(43) @ 685: uvm_test_top.env.mem_scb [mem_scoreboard] Data: a1
UVM_INFO scoreboard.sv(44) @ 685: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1158
  addr                         integral      4     'h8
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h41
  begin_time                   time          64    715
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 725: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=d, data=a1
UVM_INFO scoreboard.sv(26) @ 725: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 725: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 725: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: d
UVM_INFO scoreboard.sv(50) @ 725: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: a1 Actual Data: a1
UVM_INFO scoreboard.sv(51) @ 725: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1178
  addr                         integral      4     'h8
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hbc
  begin_time                   time          64    745
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 755: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=8, data=f6
UVM_INFO scoreboard.sv(26) @ 755: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 755: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 755: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 8
UVM_INFO scoreboard.sv(50) @ 755: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: f6 Actual Data: f6
UVM_INFO scoreboard.sv(51) @ 755: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1194
  addr                         integral      4     'h8
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h19
  begin_time                   time          64    765
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 765: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=8, data=0
UVM_INFO scoreboard.sv(26) @ 765: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 765: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 765: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 8
UVM_INFO scoreboard.sv(43) @ 765: uvm_test_top.env.mem_scb [mem_scoreboard] Data: bc
UVM_INFO scoreboard.sv(44) @ 765: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1218
  addr                         integral      4     'h9
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h6d
  begin_time                   time          64    795
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 805: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=8, data=bc
UVM_INFO scoreboard.sv(26) @ 805: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 805: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 805: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 8
UVM_INFO scoreboard.sv(50) @ 805: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: bc Actual Data: bc
UVM_INFO scoreboard.sv(51) @ 805: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1238
  addr                         integral      4     'h9
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hf3
  begin_time                   time          64    825
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 835: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=9, data=96
UVM_INFO scoreboard.sv(26) @ 835: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 835: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 835: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 9
UVM_INFO scoreboard.sv(50) @ 835: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 96 Actual Data: 96
UVM_INFO scoreboard.sv(51) @ 835: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1254
  addr                         integral      4     'h9
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h40
  begin_time                   time          64    845
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 845: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=9, data=0
UVM_INFO scoreboard.sv(26) @ 845: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 845: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 845: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 9
UVM_INFO scoreboard.sv(43) @ 845: uvm_test_top.env.mem_scb [mem_scoreboard] Data: f3
UVM_INFO scoreboard.sv(44) @ 845: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1278
  addr                         integral      4     'hf
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h85
  begin_time                   time          64    875
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 885: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=9, data=f3
UVM_INFO scoreboard.sv(26) @ 885: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 885: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 885: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 9
UVM_INFO scoreboard.sv(50) @ 885: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: f3 Actual Data: f3
UVM_INFO scoreboard.sv(51) @ 885: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1298
  addr                         integral      4     'hf
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hac
  begin_time                   time          64    905
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 915: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=f, data=ff
UVM_INFO scoreboard.sv(26) @ 915: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 915: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 915: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: f
UVM_INFO scoreboard.sv(50) @ 915: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 915: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1314
  addr                         integral      4     'hf
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h45
  begin_time                   time          64    925
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 925: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=f, data=0
UVM_INFO scoreboard.sv(26) @ 925: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 925: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 925: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: f
UVM_INFO scoreboard.sv(43) @ 925: uvm_test_top.env.mem_scb [mem_scoreboard] Data: ac
UVM_INFO scoreboard.sv(44) @ 925: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1338
  addr                         integral      4     'h4
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hcd
  begin_time                   time          64    955
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 965: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=f, data=ac
UVM_INFO scoreboard.sv(26) @ 965: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 965: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 965: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: f
UVM_INFO scoreboard.sv(50) @ 965: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ac Actual Data: ac
UVM_INFO scoreboard.sv(51) @ 965: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1358
  addr                         integral      4     'h4
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hf6
  begin_time                   time          64    985
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 995: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=4, data=ff
UVM_INFO scoreboard.sv(26) @ 995: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 995: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 995: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 4
UVM_INFO scoreboard.sv(50) @ 995: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 995: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1374
  addr                         integral      4     'h4
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hf7
  begin_time                   time          64    1005
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1005: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=4, data=0
UVM_INFO scoreboard.sv(26) @ 1005: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1005: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1005: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 4
UVM_INFO scoreboard.sv(43) @ 1005: uvm_test_top.env.mem_scb [mem_scoreboard] Data: f6
UVM_INFO scoreboard.sv(44) @ 1005: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1398
  addr                         integral      4     'h3
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h89
  begin_time                   time          64    1035
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1045: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=4, data=f6
UVM_INFO scoreboard.sv(26) @ 1045: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1045: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1045: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 4
UVM_INFO scoreboard.sv(50) @ 1045: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: f6 Actual Data: f6
UVM_INFO scoreboard.sv(51) @ 1045: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1418
  addr                         integral      4     'h3
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h14
  begin_time                   time          64    1065
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1075: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=3, data=ff
UVM_INFO scoreboard.sv(26) @ 1075: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1075: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1075: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 3
UVM_INFO scoreboard.sv(50) @ 1075: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 1075: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1434
  addr                         integral      4     'h3
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h50
  begin_time                   time          64    1085
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1085: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=3, data=0
UVM_INFO scoreboard.sv(26) @ 1085: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1085: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1085: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 3
UVM_INFO scoreboard.sv(43) @ 1085: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 14
UVM_INFO scoreboard.sv(44) @ 1085: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1458
  addr                         integral      4     'hd
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h74
  begin_time                   time          64    1115
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1125: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=3, data=14
UVM_INFO scoreboard.sv(26) @ 1125: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1125: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1125: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 3
UVM_INFO scoreboard.sv(50) @ 1125: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 14 Actual Data: 14
UVM_INFO scoreboard.sv(51) @ 1125: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1478
  addr                         integral      4     'hd
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h3d
  begin_time                   time          64    1145
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1155: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=d, data=a1
UVM_INFO scoreboard.sv(26) @ 1155: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1155: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1155: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: d
UVM_INFO scoreboard.sv(50) @ 1155: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: a1 Actual Data: a1
UVM_INFO scoreboard.sv(51) @ 1155: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1494
  addr                         integral      4     'hd
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hcc
  begin_time                   time          64    1165
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1165: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=d, data=0
UVM_INFO scoreboard.sv(26) @ 1165: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1165: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1165: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: d
UVM_INFO scoreboard.sv(43) @ 1165: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 3d
UVM_INFO scoreboard.sv(44) @ 1165: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1518
  addr                         integral      4     'h6
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h57
  begin_time                   time          64    1195
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1205: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=d, data=3d
UVM_INFO scoreboard.sv(26) @ 1205: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1205: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1205: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: d
UVM_INFO scoreboard.sv(50) @ 1205: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 3d Actual Data: 3d
UVM_INFO scoreboard.sv(51) @ 1205: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1538
  addr                         integral      4     'h6
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h85
  begin_time                   time          64    1225
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1235: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=6, data=ff
UVM_INFO scoreboard.sv(26) @ 1235: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1235: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1235: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 6
UVM_INFO scoreboard.sv(50) @ 1235: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ff Actual Data: ff
UVM_INFO scoreboard.sv(51) @ 1235: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1554
  addr                         integral      4     'h6
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hc3
  begin_time                   time          64    1245
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1245: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=6, data=0
UVM_INFO scoreboard.sv(26) @ 1245: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1245: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1245: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 6
UVM_INFO scoreboard.sv(43) @ 1245: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 85
UVM_INFO scoreboard.sv(44) @ 1245: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1578
  addr                         integral      4     'hf
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hde
  begin_time                   time          64    1275
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1285: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=6, data=85
UVM_INFO scoreboard.sv(26) @ 1285: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1285: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1285: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 6
UVM_INFO scoreboard.sv(50) @ 1285: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 85 Actual Data: 85
UVM_INFO scoreboard.sv(51) @ 1285: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1598
  addr                         integral      4     'hf
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hfc
  begin_time                   time          64    1305
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1315: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=f, data=ac
UVM_INFO scoreboard.sv(26) @ 1315: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1315: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1315: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: f
UVM_INFO scoreboard.sv(50) @ 1315: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ac Actual Data: ac
UVM_INFO scoreboard.sv(51) @ 1315: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1614
  addr                         integral      4     'hf
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h5c
  begin_time                   time          64    1325
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1325: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=f, data=0
UVM_INFO scoreboard.sv(26) @ 1325: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1325: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1325: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: f
UVM_INFO scoreboard.sv(43) @ 1325: uvm_test_top.env.mem_scb [mem_scoreboard] Data: fc
UVM_INFO scoreboard.sv(44) @ 1325: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1638
  addr                         integral      4     'h6
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hac
  begin_time                   time          64    1355
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1365: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=f, data=fc
UVM_INFO scoreboard.sv(26) @ 1365: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1365: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1365: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: f
UVM_INFO scoreboard.sv(50) @ 1365: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: fc Actual Data: fc
UVM_INFO scoreboard.sv(51) @ 1365: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1658
  addr                         integral      4     'h6
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'hc0
  begin_time                   time          64    1385
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1395: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=6, data=85
UVM_INFO scoreboard.sv(26) @ 1395: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1395: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1395: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 6
UVM_INFO scoreboard.sv(50) @ 1395: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 85 Actual Data: 85
UVM_INFO scoreboard.sv(51) @ 1395: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1674
  addr                         integral      4     'h6
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h6f
  begin_time                   time          64    1405
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1405: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=6, data=0
UVM_INFO scoreboard.sv(26) @ 1405: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1405: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1405: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 6
UVM_INFO scoreboard.sv(43) @ 1405: uvm_test_top.env.mem_scb [mem_scoreboard] Data: c0
UVM_INFO scoreboard.sv(44) @ 1405: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1698
  addr                         integral      4     'ha
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'hde
  begin_time                   time          64    1435
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1445: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=6, data=c0
UVM_INFO scoreboard.sv(26) @ 1445: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1445: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1445: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 6
UVM_INFO scoreboard.sv(50) @ 1445: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: c0 Actual Data: c0
UVM_INFO scoreboard.sv(51) @ 1445: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1718
  addr                         integral      4     'ha
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'h73
  begin_time                   time          64    1465
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1475: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=a, data=ce
UVM_INFO scoreboard.sv(26) @ 1475: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1475: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1475: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: a
UVM_INFO scoreboard.sv(50) @ 1475: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: ce Actual Data: ce
UVM_INFO scoreboard.sv(51) @ 1475: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1734
  addr                         integral      4     'ha
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h18
  begin_time                   time          64    1485
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1485: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=a, data=0
UVM_INFO scoreboard.sv(26) @ 1485: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1485: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1485: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: a
UVM_INFO scoreboard.sv(43) @ 1485: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 73
UVM_INFO scoreboard.sv(44) @ 1485: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1758
  addr                         integral      4     'he
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'ha2
  begin_time                   time          64    1515
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1525: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=a, data=73
UVM_INFO scoreboard.sv(26) @ 1525: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1525: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1525: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: a
UVM_INFO scoreboard.sv(50) @ 1525: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: 73 Actual Data: 73
UVM_INFO scoreboard.sv(51) @ 1525: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1778
  addr                         integral      4     'he
  wr_en                        integral      1     'h1
  rd_en                        integral      1     'h0
  wdata                        integral      8     'ha6
  begin_time                   time          64    1545
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1555: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=e, data=e0
UVM_INFO scoreboard.sv(26) @ 1555: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1555: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1555: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: e
UVM_INFO scoreboard.sv(50) @ 1555: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: e0 Actual Data: e0
UVM_INFO scoreboard.sv(51) @ 1555: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
------------------------------------------------------------------------------------------
Name                           Type          Size  Value
------------------------------------------------------------------------------------------
req                            mem_seq_item  -     @1794
  addr                         integral      4     'he
  wr_en                        integral      1     'h0
  rd_en                        integral      1     'h1
  wdata                        integral      8     'h19
  begin_time                   time          64    1565
  depth                        int           32    'd2
  parent sequence (name)       string        3     seq
  parent sequence (full name)  string        39    uvm_test_top.env.mem_agnt.sequencer.seq
  sequencer                    string        35    uvm_test_top.env.mem_agnt.sequencer
------------------------------------------------------------------------------------------
UVM_INFO monitor.sv(60) @ 1565: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=e, data=0
UVM_INFO scoreboard.sv(26) @ 1565: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(41) @ 1565: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO scoreboard.sv(42) @ 1565: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: e
UVM_INFO scoreboard.sv(43) @ 1565: uvm_test_top.env.mem_scb [mem_scoreboard] Data: a6
UVM_INFO scoreboard.sv(44) @ 1565: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
---------------------------------------------------
UVM_INFO monitor.sv(60) @ 1605: uvm_test_top.env.mem_agnt.monitor [MON_DEBUG] Monitor write: addr=e, data=a6
UVM_INFO scoreboard.sv(26) @ 1605: uvm_test_top.env.mem_scb [SCB_DEBUG] Data recived in scoreboard.
UVM_INFO scoreboard.sv(48) @ 1605: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: READ DATA Match :: ------
UVM_INFO scoreboard.sv(49) @ 1605: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: e
UVM_INFO scoreboard.sv(50) @ 1605: uvm_test_top.env.mem_scb [mem_scoreboard] Expected Data: a6 Actual Data: a6
UVM_INFO scoreboard.sv(51) @ 1605: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_objection.svh(1276) @ 1695: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_catcher.svh(705) @ 1695: reporter [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---


Number of demoted UVM_FATAL reports  :    0
Number of demoted UVM_ERROR reports  :    0
Number of demoted UVM_WARNING reports:    0
Number of caught UVM_FATAL reports   :    0
Number of caught UVM_ERROR reports   :    0
Number of caught UVM_WARNING reports :    0

UVM_INFO /opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_report_server.svh(894) @ 1695: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :  364
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[MON_DEBUG]    60
[RNTST]     1
[SCB_DEBUG]    60
[TEST_DONE]     1
[UVM/RELNOTES]     1
[UVM/REPORT/CATCHER]     1
[mem_scoreboard]   240

$finish called from file "/opt/Synopsys/VCS2018/vcs/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh", line 527.
$finish at simulation time                 1695
           V C S   S i m u l a t i o n   R e p o r t
Time: 1695
CPU Time:      0.390 seconds;       Data structure size:   0.5Mb
Sun Jan 18 13:27:07 2026

第三种方法是对于统一个测试逻辑，想要查看不同的随机数据，就可以通过+ntb_random_seed_auto，修改测试种子获得不同的结果。但是要注意每次都是重新运行的，会多次初始化。我们可以把run.sh改成这样：

1
2
./simv +UVM_TESTNAME=mem_model_test3 +ntb_random_seed_auto > result.log
./simv +UVM_TESTNAME=mem_model_test3 +ntb_random_seed_auto >> result.log

运行结果就是上面的结果运行之后初始化换seed在重新运行一次。

下期再见喵，Ciallo～(∠・ω< )⌒★

从零开始的DFT工程师！ homepage

project homepage is here.