从零开始的DFT工程师!
为什么要开始这个系列
开始做这个系列其实还是想要多学一点东西,感觉自己会的还是太少了,完全没有一个正常水平的数字集成电路应届毕业生的水平。而且其实差不多从大三上学期开始后我就状态低迷了一整年
现在的想法是这样的:这个学期选了自然辩证法(前八周)和集成电路前沿讲座(后八周),都是我们学校研究生的课,先多学一点,这样可以省下研一上学期的一点时间,然后多做点东西;尽早招老师开个题,毕设最好是前八周学学基础知识然后就开始做,寒假做完,在大四下学期找找实习,如果能找到的话就出去实习一个学期,找不到的话就选新中特和半导体器件这些课,给研究生在多一点时间,总体来说就是想多学一点。
我的计划是?
我计划面向实习为主,希望实习可以找一个自己喜欢的方向去做,目前觉得比较想去的就是AI处理器验证,DFT DV Engineer这个方向(其实是因为好找实习),然后也多学一些GPU图形化驱动方面的coding.
AI 处理器验证和DFT DV Engineer
- AI 处理器验证:主要负责验证功能是否正确,保证在tapeout前没有设计缺陷。
芯片验证主流的方法学是UVM(Universal Verification Methodology),他提供了一套标准化的框架和库,可以用来搭建验证环境,生成激励,并进行全面的功能覆盖。
当然有时工作还包含Post-silicon debug,芯片造出来以后发现功能不正确是就要进行流片后调试,定位并分析问题。
对于SoC验证当然需要在多了解一些总线相关知识,这个似乎比较繁杂,尽量多了解一些就可以了。
- DFT DV Engineer:Design For Test, Device Verification.
在芯片设计中提前加入特殊电路以便于在芯片制造和测试阶段高效全面的发现制造缺陷。
感觉内容比较多就不在这里写了
GPU C++ modeling
这一项属于架构探索和设计前期的工作,主要职责是构建一个高性能高精度的GPU行为级模型(感觉上来讲比前两个难一些,本科生实习也难找)。
其内容多数应该是用C++完成行为级(或以上)的软件模型构建,应该需要对体系结构,并发/超前等内容有所了解。
预计应该学习的内容
验证基础
systemverilog: testbench, interface, assertion.
UVM: verification environment, sequence, driver, monitor, coverage.
verify process: testplan -> testcase -> coverage analysis -> find bug.
SoC verification: AMBA bus(AXI,AHB,APB), peripherals.
DFT
scan chain.
ATPG.
JTAG, Boundary scan.
MBIST(memory build in itself test).
ATE bring-up.
shmoo.
screenplay
python, shell, perl.
硬件调试
FPGA/Emulator: vivado/Quartus.
Post-silicon bring-up.
GPU C++ modeling
CPU/GPU pipeline.
trace-driven/execution-driven.
并行/超前计算,SIMD, shader.
software using
verification tools
emulator: synopsys VCS / Mentor Questasim / cadence xcelium.
debugger: verdi(waveform?)
formal verification: JasperGold.
DFT tools
synopsys TetraMAX(ATPG).
DFT compiler.
mentor tessent.
design/analysis tools
design compiler, primetime, powerartist/PTPX.
GPU modeling tools.
gem5, GPGPU-sim.
学习计划
此处写一个16周和寒假学习时间表,供参考。(此处第一周实际为校历第二周)
| week | content | link | tools |
|---|---|---|---|
| 1 | verilog+systemverilog | week 1 | verilog: iverilog + gtkwave vivado systemverilog: cadence virtuoso + simvision + incisive slang + UHDM + surlog + yosys + verilator |
| 2 | makefile/python + tcl/cmake/jenkins | week 2 | makefile/cmake/python/tcl |
| 3 | DFT&EDA foundation | week 3 | verilog/systemverilog |
| 4 | UVM verification (env/driver/monitor/scoreboard) |
week 4 | UVM lib + systemverilog |
| 5 | AI accelerator verification pipeline/hazard/stall/forwarding |
week 5 | verilog+systemverilog |
| 6 | Assertions &Coverage SVA, functional coverage |
week 6 | verilog + systemverilog |
| 7 | GPU C++/CUDA kernel/memory/hierarchy |
week 7 | CUDA Toolkit + Nsight |
| 8 | insert scan chain in opensource CPU/SoC | week 8 | verilog + systemverilog |
| 9 | fault coverage analysis stuck-at/trascation-fault |
week 9 | verilog + systemverilog |
| 10 | AI accelerator verification: systolic array |
week 10 | verilog + python + golden model |
| 11 | GPU C++ project contain shared memory optimization |
week11 | CUDA Toolkit |
| 12 | randomized stimulus + coverage-driven verification | week 12 | UVM + incisive |
| 13 | git CI/CD + python + tcl auto-verify | week 13 | Gitlab CI/jenkins/GitHub Actions |
| 14 | verification: MBIST/JTAG/Boundary scan low power verification: UPF/CPF/clock gating/power domain |
week 14 | none |
| 15 | log parser/coverage report generator | week 15 | none |
| 16 | opensource: emulator: verilator + iverilog synthesize&STA: yosys, opensta P&R: OpenROAD verification architecture: cocotb/UVM-lite |
week 16 | too much to write, see in the link |
| 17(option) | graphic foundation: OpenGL/DirectX Vulkan GPU SIMT |
week 17 | none |
| 18 | GPU C++ performance modeling and analysis | week 18 | modeling: GPGPU-sim gem5-gpu Accelsim analysis: NVIDIA Nsight Compute Nsight Systems |
| 特别篇1 | synopsys 工具组的安装 | synopsys install | none |
| 特别篇2 | systemverilog | sv&vcs | systemverilog vcs |
| 21 | |||
| 22 |
此处我展示一个DFT工程师招聘要求:





